The present invention is directed to memory management units of a digital processing system, in general, and more particular, to a memory management unit (MMU) which includes programmable descriptors corresponding to segmented portions of physical memory to indicate whether or not each segmented memory portion is protected by error detection and correction (EDAC) codes.
In most modem digital processing systems, digital words are comprised of many bytes, i.e. 8-bit sections. For example, most microprocessor systems today operate with 32 bit words. The more powerful ones operate with 64 bit words. As the bits per word increase, so does the chance of an error occurring during storage and transmission of these lengthy words between processing sections. Some systems have added error detection and correction (EDAC) codes to the digital words that are stored and transferred with them for checking at the transfer destination. Generally, with these type codes, the processor may detect and correct a single error in the transmitted word and detect multiple errors to provide an indication of bad received data. But not all external devices or input/output (I/O) devices coupled to a processor should be required to have the capability to generate and check EDAC codes. Accordingly, some devices may have EDAC capability and others not. Mixing EDAC capable devices with those that are not EDAC capable cause complex problems at the system design level and may also impact system performance and cost.
Currently, the processing systems that use EDAC codes, but also have devices that do not support EDAC capability, generally require that the processor turn off or deactivate the EDAC checking circuitry when communicating with non EDAC supporting devices. The overhead required for the processor to reactivate the EDAC circuitry become burdensome and deactivating the EDAC circuitry removes the protection of the code while a data transfer is performed to a non-EDAC protected device. Systems that require writing to devices that have less than the width of one word, for example a byte wide device in a 32-bit bus system, are generally required to have EDAC protection down to the smallest accessible transfer width, usually one byte. This type of protection is costly from a monetary, power consumption and board real-estate perspective. Systems that use a single EDAC code consisting of one or more bits to cover a multi-byte word are severely impacted in performance when operating on sub-word transfers. In such systems, since the EDAC code applies to the entire multi-byte word, sub-word operations can not be performed with the EDAC circuitry activated without additional hardware or software resource added to the system to perform these operations.
The processor should make the determination of the type of EDAC protection to apply, based on system design parameters. If the EDAC code is not generated and attached by the processor and the device can process EDAC codes, then the system runs the risk of an error in transmission. On the other hand, when the external device is the source of transmission, the processor should know if the EDAC code is valid, (i.e. the external device can generate EDAC code).
One solution could be to make all external devices and memory systems capable of generating and checking EDAC codes, but this would lead to an expensive system overall. On the other hand, by offering the ability to segment EDAC protection functionality across a complete system address space, costs may be significantly reduced by not forcing EDAC protection onto address sections that do not inherently require the additional protection. One example of a system that may not require EDAC protection is a serial interface that has a built in protection system in data supplied in the form of a cyclic redundancy check (CRC) error correcting code. A more cost effective solution for moving data of this type would be to transfer the data with peripheral systems that do not have EDAC protection and to place the data into an EDAC protected memory internally to the processing system. Once the data is in the protected memory, it can be evaluated for errors and corrected using its own CRC codes. The resulting data would then be protected and maintained in a fault protected environment using EDAC codes built on the memory. The problem with placing devices within the processor system that support EDAC and other fault tolerant features in different ways should be solved without impacting performance, flexibility and operational capability of the system.
The present invention is intended to provide a processing system that has the flexibility of performing EDAC protection over various segmented sections of memory space. Such a processing system allows maximum performance at a lower cost by permitting a mix of both EDAC and non-EDAC protected devices located within a common memory space of the system.
In accordance with one aspect of the present invention, a memory management unit (MMU) of a digital processing system operating in a virtual address domain and a physical address domain comprises a memory programmable to store translation mappings between virtual addresses and physical addresses of said processing system; said memory also programmable to store control codes representative of EDAC protection corresponding to the translation mappings.
In accordance with another aspect of the present invention, a method of operating a memory management unit (MMU) of a digital processing system operable in both virtual and physical address domains wherein the method comprises the steps of: programming a memory of the MMU with virtual to physical address translation mappings; and programming the memory of the MMU with control codes representative of EDAC protection corresponding to said translation mappings.